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Disambiguation of "Joshi, Ajay"

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Nile: A Programmable Monitoring Coprocessor.

, , , , and . IEEE Comput. Archit. Lett., 17 (1): 92-95 (2018)

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Ajay Chavan

Godwin Olu Ajayi

Jidnyasa Joshi

Ajay Moza

Ajay Wakhloo

 

Other publications of authors with the same name

Neural network-based accelerators for transcendental function approximation., , , and . ACM Great Lakes Symposium on VLSI, page 169-174. ACM, (2014)Sub-threshold logic circuit design using feedback equalization., and . DATE, page 1-6. European Design and Automation Association, (2014)Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes., , and . DSN, page 41-50. IEEE Computer Society, (2010)Network-on-Chip Microarchitecture-based Covert Channel in GPUs., , , , , , , and . MICRO, page 565-577. ACM, (2021)NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator., , , , , , , and . ISCA, page 946-960. IEEE, (2024)Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (9): 990-1002 (2007)Thermal management of manycore systems with silicon-photonic networks., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes., , , and . ICICS, volume 5927 of Lecture Notes in Computer Science, page 47-62. Springer, (2009)Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 899-910 (2005)FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption., , , , , , , and . HPCA, page 882-895. IEEE, (2023)