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A 6-12GHz Wideband Programmable Phase-Locked Loop in 65 nm CMOS.

, , and . ICCT, page 1015-1019. IEEE, (2019)

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A 6-12GHz Wideband Programmable Phase-Locked Loop in 65 nm CMOS., , and . ICCT, page 1015-1019. IEEE, (2019)Particle flow code method-based seepage behavior analysis and control effect evaluation for soil levee., , , and . Eng. Comput., 36 (1): 97-114 (2020)Improved PLS and PSO methods-based back analysis for elastic modulus of dam., , and . Adv. Eng. Softw., (2019)BIST approach for testing configurable logic and memory resources in FPGAs., , , , and . APCCAS, page 1767-1770. IEEE, (2008)Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)., , , , and . FPGA, page 254. ACM, (2014)SFPSO algorithm-based multi-scale progressive inversion identification for structural damage in concrete cut-off wall of embankment dam., , and . Appl. Soft Comput., (2019)Method for Choosing the Optimal Resource in Back-Analysis for Multiple Material Parameters of a Dam and Its Foundation., , , and . J. Comput. Civ. Eng., (2016)A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA., , , , and . ReConFig, page 1-5. IEEE Computer Society, (2009)A configurable fault-tolerant glitch-free clock switching circuit., , , , , , and . MWSCAS, page 537-540. IEEE, (2013)A Novel Digital DLL and Its Implement on the FPGA., , , and . IMECS, page 1789-1792. Newswood Limited, (2007)