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Physical Synthesis with Clock-Network Optimization for Large Systems on Chips., , , , , , and . IEEE Micro, 31 (4): 51-62 (2011)Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits.. University of Michigan, USA, (2010)RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm., , , , , , , and . ISPD, page 2-9. ACM, (2008)Early research experience with OpenAccess gear: an open source development environment for physical design., , , , , , and . ISPD, page 94-100. ACM, (2005)Pyramids: an efficient computational geometry-based approach for timing-driven placement., , , , , and . ICCAD, page 204-211. IEEE Computer Society, (2008)Unification of partitioning, placement and floorplanning., , , , and . ICCAD, page 550-557. IEEE Computer Society / ACM, (2004)Path smoothing via discrete optimization., , , and . DAC, page 724-727. ACM, (2008)Quantifying academic placer performance on custom designs., , , , , and . ISPD, page 91-98. ACM, (2011)Constructive benchmarking for placement., , and . ACM Great Lakes Symposium on VLSI, page 113-118. ACM, (2004)Capo: robust and scalable open-source min-cut floorplacer., , , , , , and . ISPD, page 224-226. ACM, (2005)