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Disambiguation of "Roy, Subir K."

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Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces.

, and . J. Electron. Test., 29 (5): 715-740 (2013)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

K Dutta-Roy

Günter Subirge

Roy Hornig

Beschreibung mikro-rheologischer Vorgänge und resultierender Verbundstrukturen beim Elastomermischprozeß im Innenmischer durch rheologische Untersuchungen. NA Halle-Wittenberg, (2009)

Smritindu Roy

David Roy

 

Other publications of authors with the same name

Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract)., , , , and . ASP-DAC/VLSI Design, page 11-13. IEEE Computer Society, (2002)Formal verification based on assume and guarantee approach - a case study (short paper)., , and . ASP-DAC, page 77-80. ACM, (2000)Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs., and . VLSI Design, page 364-372. IEEE Computer Society, (2007)Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach., , and . MFCS, volume 841 of Lecture Notes in Computer Science, page 525-535. Springer, (1994)Formal verification of switched capacitor DC to DC power converter using circuit simulation traces., and . VDAT, page 1-2. IEEE, (2016)Dataflow Analysis for Resource Contention and Register Leakage Properties., , and . VLSI Design, page 418-423. IEEE Computer Society, (2000)Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine., and . ISCAS, page 2564-2567. IEEE, (1993)Top Level SOC Interconnectivity Verification Using Formal Techniques.. MTV, page 63-70. IEEE Computer Society, (2007)DFT logic verification through property based formal methods - SOC to IP., , , , and . FMCAD, page 33. IEEE, (2010)Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces., and . J. Electron. Test., 29 (5): 715-740 (2013)