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Disambiguation of "Sondeen, Jeff"

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Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems.

, , and . ISCAS (4), page 3331-3334. IEEE, (2005)

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Jeff Berens

Jeff Bezanson

Dennis Jeffrey

Jeff Jay

Jeff Tian

 

Other publications of authors with the same name

An area-efficient standard-cell floating-point unit design for a processing-in-memory system., , , and . ESSCIRC, page 57-60. IEEE, (2003)A 0.18 µm implementation of a floating-point unit for a processing-in-memory system., , , and . ISCAS (2), page 453-456. IEEE, (2004)Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems., , and . ISCAS (4), page 3331-3334. IEEE, (2005)An area-efficient and protected network interface for processing-in-memory systems., , , and . ISCAS (3), page 2951-2954. IEEE, (2005)Floating-point division and square root implementation using a Taylor-series expansion algorithm., , and . ICECS, page 702-705. IEEE, (2008)Multicast routing with dynamic packet fragmentation., , and . ACM Great Lakes Symposium on VLSI, page 113-116. ACM, (2009)A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability., , , , , , and . ISCAS, IEEE, (2006)A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System., , , , , , and . VLSI Signal Processing, 40 (1): 73-84 (2005)An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System., , and . VLSI Design, page 863-868. IEEE Computer Society, (2004)Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip., , , and . ASAP, page 163-172. IEEE Computer Society, (2002)