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Disambiguation of "Raychowdhury, Arijit"

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High efficiency power side-channel attack immunity using noise injection in attenuated signature domain.

, , , , , and . HOST, page 62-67. IEEE Computer Society, (2017)

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Arijit Ghosh

Arijit Kundu

Arijit Maitra

Arijit Biswas

Arijit Mukherjee

 

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A Survey of FPGA-Based Robotic Computing., , , , , , , and . CoRR, (2020)EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 4:1-4:17 (2022)OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers., , , and . IEEE J. Solid State Circuits, 55 (3): 629-638 (2020)Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion., , , and . VLSI-SOC, page 208-209. IEEE, (2020)Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity., and . VLSI-SoC, page 1-2. IEEE, (2022)Reducing Overhead of Feature Importance Visualization via Static GradCAM Computation., and . AICAS, page 1-5. IEEE, (2023)An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform., , , , , and . AICAS, page 1-4. IEEE, (2021)A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee., , and . ISSCC, page 488-489. IEEE, (2021)A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , and . ISSCC, page 1-3. IEEE, (2022)