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Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

H. Cai, H. Jiang, Y. Zhou, M. Han, and B. Liu. CCF Trans. High Perform. Comput., 2 (3): 282-296 (2020)

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Yongliang Huang

Zhou Zhou

Jiyang Zhou

Zuliang Zhou

Other publications of authors with the same name

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.L. Hao, X. Zhang, C. Dai, Q. Zhao, W. Lu, C. Peng, Y. Zhou, Z. Lin, and X. Wu. IEEE Trans. Very Large Scale Integr. Syst., 32 (4): 597-608 (April 2024)Rank-two residue iteration method for nonnegative matrix factorization.H. Liu, and Y. Zhou. Neurocomputing, 74 (17): 3305-3312 (2011)Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection.S. Shen, H. Xu, Y. Zhou, M. Ling, and W. Yu. CoRR, (2023)ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.A. Guo, Y. Zhou, B. Wang, T. Xiong, C. Xue, Y. Wang, X. Si, and J. Yang. ISCAS, page 2276-2280. IEEE, (2022)Writing-only in-MRAM computing paradigm for ultra-low power applications.B. Liu, M. Liu, Y. Zhou, X. Hong, H. Cai, and L. de Barros Naviner. Microprocess. Microsystems, (April 2022)Magnetic Tunnel Junction Applications.N. Maciel, E. Marques, L. Naviner, Y. Zhou, and H. Cai. Sensors, 20 (1): 121 (2020)MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.Y. Zhou, H. Cai, B. Liu, W. Zhao, and J. Yang. IEEE Trans. Circuits Syst., 67-II (12): 3352-3356 (2020)A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators.Y. Zhou, Z. Cheng, H. Liu, T. Xiong, and B. Wang. APCCAS, page 501-504. IEEE, (2022)Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices.X. Si, Y. Zhou, J. Yang, and M. Chang. ASICON, page 1-4. IEEE, (2021)Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.L. Hao, Y. Wang, Y. Liu, S. Zhao, X. Zhang, Y. Li, W. Lu, C. Peng, Q. Zhao, Y. Zhou and 3 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 32 (5): 883-896 (May 2024)

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Disambiguation of "Zhou, Yongliang"

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Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

Please choose a person to relate this publication to

Yongliang Huang

Zhou Zhou

Zhou Zhou

Jiyang Zhou

Zuliang Zhou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhou, Yongliang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

Please choose a person to relate this publication to

Yongliang Huang

Zhou Zhou

Zhou Zhou

Jiyang Zhou

Zuliang Zhou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.