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Microarchitectural optimization by means of reconfigurable and evolvable cache mappings.

, , , and . AHS, page 1-7. IEEE, (2015)

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Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) Editorial., , and . IET Comput. Digit. Tech., 4 (3): 157-158 (2010)Evolution of application-specific cache mappings., , and . Int. J. Hybrid Intell. Syst., 16 (3): 149-161 (2020)Enabling XCSF to cope with dynamic environments via an adaptive error threshold., , and . GECCO Companion, page 125-126. ACM, (2020)Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection., and . ARC, volume 8405 of Lecture Notes in Computer Science, page 283-290. Springer, (2014)Using Deep Convolutional Neural Networks in Monte Carlo Tree Search., and . Computers and Games, volume 10068 of Lecture Notes in Computer Science, page 11-21. Springer, (2016)Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan., , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 127-136. Springer, (2019)Online Scheduling for Block-Partitioned Reconfigurable Devices ., and . DATE, page 10290-10295. IEEE Computer Society, (2003)Aktuelles Schlagwort: Approximate Computing, , and . Informatik Spektrum, (October 2015)Towards Multi-movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets, , , and . (2009)FPGA Redundancy Configurations: An Automated Design Space Exploration., , and . IPDPS Workshops, page 275-280. IEEE Computer Society, (2014)