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Microarchitectural optimization by means of reconfigurable and evolvable cache mappings.

, , , and . AHS, page 1-7. IEEE, (2015)

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Parallel Qualitative Simulation., , and . EUROSIM, page 231-236. Elsevier, (1995)A Special-purpose Coprocessor for Qualitative Simulation., , and . Euro-Par, volume 966 of Lecture Notes in Computer Science, page 695-698. Springer, (1995)Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus., and . Microprocess. Microsystems, (2017)On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach., , and . ARC, volume 9040 of Lecture Notes in Computer Science, page 365-372. Springer, (2015)ReconROS: Flexible Hardware Acceleration for ROS2 Applications., , and . FPT, page 268-276. IEEE, (2020)Search space characterization for approximate logic synthesis., , , and . DAC, page 433-438. ACM, (2022)A Runtime Environment for Reconfigurable Hardware Operating Systems., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 831-835. Springer, (2004)Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array., and . EMBC, page 4324-4327. IEEE, (2012)Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity., and . EMBC, page 4547-4550. IEEE, (2014)Comparison of thread signatures for error detection in hybrid multi-cores., and . FPT, page 212-215. IEEE, (2015)