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Disambiguation of "Flynn, Michael P."

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A 4GS/s 4b Flash ADC in 0.18µm CMOS.

, , and . ISSCC, page 2330-2339. IEEE, (2006)

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Robynne Flynn-Diez

Choi-Yeung-Chang Flynn

Sharon Flynn

Linda Jessica Flynn

Michael P Maier

 

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A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (7): 2269-2278 (2018)Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System., and . IEEE J. Solid State Circuits, 53 (6): 1719-1730 (2018)A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme., and . IEEE J. Solid State Circuits, 43 (11): 2464-2471 (2008)An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS., , and . ESSCIRC, page 238-241. IEEE, (2010)Design techniques for high performance CMOS flash analog-to-digital converters., and . ECCTD, page 131-134. IEEE, (2005)An N-path filter enhanced low phase noise ring VCO., , , and . VLSIC, page 1-2. IEEE, (2014)A 16-channel noise-shaping machine learning analog-digital interface., , , , and . VLSI Circuits, page 1-2. IEEE, (2016)A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS., and . CICC, page 337-340. IEEE, (2007)A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination., , and . ESSCIRC, page 233-236. IEEE, (2012)A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction., , , , and . CICC, page 1-2. IEEE, (2021)