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Analysis and design of digital PRNGS based on the discretized sawtooth map.

, , , , and . ICECS, page 427-430. IEEE, (2003)

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Efficient and Accurate Models of Output Transition Time in CMOS Logic., , and . ICECS, page 1264-1267. IEEE, (2007)Analysis of the impact of random process variations in CMOS tapered buffers., , and . ICECS, page 57-60. IEEE, (2009)Analysis of the impact of process variations on static logic circuits versus fan-in., , and . ICECS, page 137-140. IEEE, (2008)Energy evaluation in RLC tree circuits with exponential input., , and . ICECS, page 578-581. IEEE, (2008)Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders., and . ICECS, page 518-521. IEEE, (2006)A closed-form energy model for VLSI circuits under wide voltage scaling., and . ICECS, page 548-551. IEEE, (2016)Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis., , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 624-633. Springer, (2006)Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V., , and . ISCAS, page 1-5. IEEE, (2018)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 737-750 (2011)Evaluation of energy consumption in RC ladder circuits driven by a ramp input., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (10): 1094-1107 (2004)