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Design methodology for the IBM POWER7 microprocessor., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 55 (3): 9 (2011)Clock period constrained minimal buffer insertion in clock trees., and . ICCAD, page 219-223. IEEE Computer Society / ACM, (1994)On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques., , and . ISPD, page 152-159. ACM, (2018)LEO: Line End Optimizer for Sub-7nm Technology Nodes., , and . ISPD, page 117-125. ACM, (2022)On Rectilinear Distance-Preserving Trees., and . ISCAS, page 163-166. IEEE, (1995)Unification of Budgeting and Placement., , and . DAC, page 758-761. ACM Press, (1997)A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation., , and . ISPD, page 116-121. ACM, (1997)Memory Segmentation to Exploit Sleep Mode Operation., , and . DAC, page 36-41. ACM Press, (1995)GLARE: global and local wiring aware routability evaluation., , , , , , , , , and . DAC, page 768-773. ACM, (2012)Interconnect Optimization Considering Multiple Critical Paths., , , , , , and . ISPD, page 132-138. ACM, (2018)