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Disambiguation of "Shieh, Ming-Der"

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An area-efficient systolic division circuit over GF(2m) for secure communication.

, , , and . ISCAS (5), page 733-736. IEEE, (2002)

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Ming-Yan Shieh

Shu-Mei Shieh

Woei-Chyang Shieh

Jin-Wien Shieh

Pi-Er Shieh

 

Other publications of authors with the same name

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers., , , , and . DDECS, page 1-4. IEEE, (2019)Subspace-Based Blind Channel Estimation for MIMO-OFDM Systems with Repetition Index., , , , , and . VTC Fall, page 1-5. IEEE, (2013)Efficient Memory-Addressing Algorithms for FFT Processor Design., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2162-2172 (2015)A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem., , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1151-1161 (2008)Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders., , and . IEICE Trans. Inf. Syst., 91-D (9): 2300-2311 (2008)High-Speed Design of Montgomery Inverse Algorithm over GF(2m)., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (2): 559-565 (2006)A New Algorithm for High-Speed Modular Multiplication Design., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2009-2019 (2009)Low-complexity Reed-Solomon decoder for optical communications., , and . ISCAS, page 4173-4176. IEEE, (2010)An efficient countermeasure against power attacks for ECC over GF(p)., , and . ISCAS, page 814-817. IEEE, (2014)Efficient path metric access for reducing interconnect overhead in Viterbi decoders., , , and . ISCAS, IEEE, (2006)