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Disambiguation of "Yanagisawa, Masao"

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2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement.

, , , and . NGCAS, page 182-185. IEEE, (2018)

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Masao Sekine

Masao Watanabe

Masao Tanaka

Mohamed Abdul-Jalil Ahmed Masaoud

Fidelis Taliwawa Masao

 

Other publications of authors with the same name

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures., , and . ISCAS, page 576-579. IEEE, (2012)Weighted adders with selector logics for super-resolution and its FPGA-based evaluation., , and . APCCAS, page 603-606. IEEE, (2012)A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration., , and . APCCAS, page 248-251. IEEE, (2014)A hardware-Trojan classification method utilizing boundary net structures., , and . ICCE, page 1-4. IEEE, (2018)Road-illuminance level inference across road networks based on Bayesian analysis., , and . ICCE, page 1-6. IEEE, (2018)Clock skew estimate modeling for FPGA high-level synthesis and its application., , , and . ASICON, page 1-4. IEEE, (2015)Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (4): 1015-1028 (2017)A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (7): 1025-1034 (2018)Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2484-2493 (2015)A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3218-3224 (2003)