( en | de | ru )

 

Disambiguation of "Barke, Erich"

Author of the publication

copydeleteadd this publication to your clipboard
3D floorplanning considering vertically aligned rectilinear modules using T∗-tree.

, , , and . 3DIC, page 1-5. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Erich Barke

August Barke

Inka Barke

Herbert Barke

August Barke

 

Other publications of authors with the same name

A Universal CLA Adder Generator for SRAM-Based FPGAs., and . FPL, volume 1142 of Lecture Notes in Computer Science, page 44-54. Springer, (1996)PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor., , and . ED&TC, page 357-361. IEEE Computer Society, (1996)Architecture driven partitioning., and . DATE, page 479-487. IEEE Computer Society, (2001)Resistance calculation from mask artwork data by finite element method.. DAC, page 305-311. ACM, (1985)Static Timing Analysis Taking Crosstalk into Account., , and . DATE, page 451-455. IEEE Computer Society / ACM, (2000)A New Placement Method for Direct Mapping into LUT-Based FPGAs., and . FPL, volume 2147 of Lecture Notes in Computer Science, page 27-36. Springer, (2001)Path Verification Using Boolean Satisfiability., , and . DATE, page 965-966. IEEE Computer Society, (1998)Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle., , , and . MBMV, page 191-200. Fraunhofer Institut für Integrierte Schaltungen, (2006)Real Time Fault Injection Using Logic Emulators., and . ASP-DAC, page 475-479. IEEE, (1998)An extended bipolar transistor model for substrate crosstalk analysis., and . CICC, page 579-582. IEEE, (1999)