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Production Recipe Validation through Formalization and Digital Twin Generation., , , , and . DATE, page 1698-1703. IEEE, (2020)Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress., , , and . CODES+ISSS, page 4. IEEE / ACM, (2018)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1702-1715 (2017)A SystemC-based platform for assertion-based verification and mutation analysis in systems biology., , , , , , and . LATS, page 159-164. IEEE, (2016)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)A fault tolerant incremental design methodology., , and . ISCAS (3), page 161-164. IEEE, (2002)On the automatic synthesis of parallel SW from RTL models of hardware IPs., , , and . ACM Great Lakes Symposium on VLSI, page 71-74. ACM, (2012)A timing-accurate modeling and simulation environment for networked embedded systems., , , , , and . DAC, page 42-47. ACM, (2003)Abstraction of RTL IPs into embedded software., , and . DAC, page 24-29. ACM, (2010)