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Disambiguation of "Singh, Ullas"

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A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.

, , , , , , , , and . ISSCC, page 32-33. IEEE, (2013)

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Sohan Singh

Sudhir Singh

Arunoday Singh

Sikander Singh

Raminder Singh

 

Other publications of authors with the same name

New structures for very high-frequency CMOS clock dividers., and . ISCAS (4), page 622-625. IEEE, (2001)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 51 (4): 881-892 (2016)An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology., , , , , , , , , and 12 other author(s). ISSCC, page 120-122. IEEE, (2022)2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS., , , , , , , and . ISSCC, page 40-41. IEEE, (2014)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)Design of CMOS CML circuits for high-speed broadband communications., and . ISCAS (2), page 204-207. IEEE, (2003)Dynamics of high-frequency CMOS dividers., and . ISCAS (5), page 421-424. IEEE, (2002)A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS., , and . IEEE J. Solid State Circuits, 41 (9): 2067-2076 (2006)A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS., , , , , , , and . VLSIC, page 1-2. IEEE, (2014)3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)