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Improving Multi-Application Concurrency Support Within the GPU Memory System., , , , , , , and . CoRR, (2017)Practical Resilience Analysis of GPGPU Applications in the Presence of Single- and Multi-Bit Faults., , , and . IEEE Trans. Computers, 70 (1): 30-44 (2021)Analyzing and Leveraging Decoupled L1 Caches in GPUs., , , , and . HPCA, page 467-478. IEEE, (2021)OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance., , , , , , , and . ASPLOS, page 395-406. ACM, (2013)RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing Techniques., , and . HPCA, page 156-167. IEEE Computer Society, (2018)Architectural Support for Efficient Large-Scale Automata Processing., , , , and . MICRO, page 908-920. IEEE Computer Society, (2018)Quantifying Data Locality in Dynamic Parallelism in GPUs., , , , , and . SIGMETRICS (Abstracts), page 25-26. ACM, (2019)Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM., and . DSN, page 362-374. IEEE, (2019)A Regression-based Model for End-to-End Latency Prediction for DNN Execution on GPUs., , and . ISPASS, page 343-345. IEEE, (2023)Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File., , , and . VLSID, page 409-414. IEEE Computer Society, (2017)