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Disambiguation of "Shanbhag, Naresh R."

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Pipelined Adaptive IIR Filter Architecture.

, and . ISCAS, page 558-561. IEEE, (1995)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

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An In-Memory VLSI Architecture for Convolutional Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)Statistical information processing: Computing for the nanoscale era.. ISLPED, page 1. IEEE, (2015)Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm., and . CoRR, (2018)Analytical Guarantees on Numerical Precision of Deep Neural Networks., , and . ICML, volume 70 of Proceedings of Machine Learning Research, page 3007-3016. PMLR, (2017)Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)., and . ICASSP, page 3081-3084. IEEE, (1998)A sphere decoding approach for the vector Viterbi algorithm., , , and . ACSCC, page 114-118. IEEE, (2012)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , and . ESSCIRC, page 263-266. IEEE, (2017)An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks., , , and . ICASSP, page 1037-1041. IEEE, (2015)Design methodology for high-speed iterative decoder architectures., and . ICASSP, page 3085-3088. IEEE, (2002)Coordinated Science Laboratory 70th Anniversary Symposium: The Future of Computing., , , , , , , , , and 18 other author(s). CoRR, (2022)