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Disambiguation of "Viñals, Víctor"

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Store Buffer Design in First-Level Multibanked Data Caches.

, , , and . ISCA, page 469-480. IEEE Computer Society, (2005)

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Víctor Farías

Víctor Castaño

Víctor Jiménez

Víctor Uc-Cetina

Reinforcement learning in continuous state and action spaces. HU Berlin, (2009)

Víctor Olmos León

 

Other publications of authors with the same name

Light NUCA: A proposal for bridging the inter-cache latency gap., , , , and . DATE, page 530-535. IEEE, (2009)Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation., , , , , and . IEEE PACT, page 170-181. IEEE Computer Society, (2003)Delaying Physical Register Allocation through Virtual-Physical Registers., , , , and . MICRO, page 186-192. ACM/IEEE Computer Society, (1999)Hardware Schemes for Early Register Release., , , and . ICPP, page 5-13. IEEE Computer Society, (2002)Microarchitectural Support for Speculative Register Renaming., , , and . IPDPS, page 1-10. IEEE, (2007)Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems., , , and . RTCSA, page 319-328. IEEE Computer Society, (2010)ReD: A reuse detector for content selection in exclusive shared last-level caches., , , , and . J. Parallel Distributed Comput., (2019)MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array., , , , , , , , , and 1 other author(s). ICECS, page 1-5. IEEE, (2023)Contents Management in First-Level Multibanked Data Caches., , , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 516-524. Springer, (2004)Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs., , , , , and . HPCA, page 179-192. IEEE, (2023)