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A coarse-grained reconfigurable computing architecture with loop self-pipelining.

Y. Dou, G. Wu, J. Xu, and X. Zhou. Sci. China Ser. F Inf. Sci., 52 (4): 575-587 (2009)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Jinjin Wu

Changzhu Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.Y. Dou, J. Xu, and G. Wu. ARC, volume 4419 of Lecture Notes in Computer Science, page 155-166. Springer, (2007)Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.J. Xu, G. Wu, Y. Dou, and Y. Dong. Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 567-573. Springer, (2006)A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519.G. Wu, Q. He, J. Jiang, Z. Zhang, X. Long, Y. Zhao, and Y. Zou. FCCM, page 1-9. IEEE, (2022)A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.G. Wu, Y. Dou, Y. Lei, J. Zhou, M. Wang, and J. Jiang. FCCM, page 183-190. IEEE Computer Society, (2009)Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors.M. Wang, G. Wu, and Z. Wang. ISPA, volume 4742 of Lecture Notes in Computer Science, page 946-957. Springer, (2007)Automatic synthesis of processor arrays with local memories on FPGAs.G. Wu, Y. Dou, and M. Wang. FPT, page 249-252. IEEE, (2010)A coarse-grained reconfigurable computing architecture with loop self-pipelining.Y. Dou, G. Wu, J. Xu, and X. Zhou. Sci. China Ser. F Inf. Sci., 52 (4): 575-587 (2009)High performance and memory efficient implementation of matrix multiplication on FPGAs.G. Wu, Y. Dou, and M. Wang. FPT, page 134-137. IEEE, (2010)FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.Y. Dou, Y. Lei, G. Wu, S. Guo, J. Zhou, and L. Shen. ICS, page 325-336. ACM, (2010)Topgun: An ECC Accelerator for Private Set Intersection.G. Wu, Q. He, J. Jiang, Z. Zhang, Y. Zhao, Y. Zou, J. Zhang, C. Wei, Y. Yan, and H. Zhang. ACM Trans. Reconfigurable Technol. Syst., 16 (4): 52:1-52:30 (December 2023)

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Disambiguation of "Wu, Guiming"

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A coarse-grained reconfigurable computing architecture with loop self-pipelining.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Changzhu Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Guiming"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A coarse-grained reconfigurable computing architecture with loop self-pipelining.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Changzhu Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A coarse-grained reconfigurable computing architecture with loop self-pipelining.