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Disambiguation of "Pizano-Escalante, Luis"

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Modular Arithmetic CPM for SDR Platforms.

, , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2111-2115 (2022)

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Werner Luis

José Escalante

Pia Luislampe

Mathieu Luisier

Werner Luis

 

Other publications of authors with the same name

On-chip implementation of a low-latency bit-accurate reciprocal square root unit., , , , and . Integr., (2018)Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology., , and . LATINCOM, page 1-5. IEEE, (2018)Application of Machine Learning Techniques to Characterize Floating Point Benchmarks using Hardware Events., , and . CCE, page 1-6. IEEE, (2023)Modular Arithmetic CPM for SDR Platforms., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2111-2115 (2022)Fast bit-accurate reciprocal square root., , , and . Microprocess. Microsystems, 39 (2): 74-82 (2015)Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation., , , , and . ReConFig, page 1-6. IEEE, (2013)Simulation Model to Predict BER Based on S-Parameters of High-Speed Interconnects., , , and . IEEE Des. Test, 36 (1): 31-39 (2019)IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core., , , , and . LATINCOM, page 1-6. IEEE, (2018)