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Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.

, , , , , and . ICCD, page 106-113. IEEE Computer Society, (1993)

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Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area.. ICCD, page 360-363. IEEE, (2022)A Front-End Execution Architecture for High Energy Efficiency., , and . MICRO, page 419-431. IEEE Computer Society, (2014)Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.. MICRO, page 82-94. IEEE Computer Society, (2018)An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism., , , , and . EUROMICRO, page 1432-1440. IEEE Computer Society, (1999)FXA: Executing Instructions in Front-End for Energy Efficiency., , , and . IEICE Trans. Inf. Syst., 99-D (4): 1092-1107 (2016)Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine., , , , , and . ICCD, page 106-113. IEEE Computer Society, (1993)Unconstrained Speculative Execution with Predicated State Buffering., , , and . ISCA, page 126-137. ACM, (1995)SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.. MICRO, page 506-518. ACM, (2019)Reducing register file size through instruction pre-execution enhanced by value prediction., and . ICCD, page 238-245. IEEE Computer Society, (2009)Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation., , , and . Inf. Media Technol., 3 (4): 755-767 (2008)