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Block-based frequency scalable technique for efficient hierarchical coding.

, , , and . IEEE Trans. Signal Process., 54 (7): 2559-2566 (2006)

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High Performance Array Processor for Video Decoding., , and . ISVLSI, page 28-33. IEEE Computer Society, (2005)Efficient VLSI implementation of inverse discrete cosine transform image coding applications., , and . ICASSP (5), page 177-180. IEEE, (2004)Hardware Multi-Threaded System for High-Performance JPEG Decoding., and . J. Signal Process. Syst., 96 (1): 67-79 (January 2024)An Architecture for Motion Estimation in the Transform Domain., , , and . VLSI Design, page 1077-1082. IEEE Computer Society, (2004)Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC., , and . Intell. Autom. Soft Comput., 23 (2): 365-371 (2017)A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration., and . ICASSP, page 1566-1569. IEEE, (2010)A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration., and . ERSA, page 219-225. CSREA Press, (2009)Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors., , , , , , and . ERSA, page 49-58. CSREA Press, (2010)Fault Demotion Using Reconfigurable Slack (FaDReS)., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1364-1368 (2013)Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study., , and . ERSA, page 313-314. CSREA Press, (2008)