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Retargetable pipeline hazard detection for partially bypassed processors.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (8): 791-801 (2006)

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An Approach to Combine Predicated/Speculative Execution for Programs with Unpredictable Branches., , and . IFIP PACT, volume A-50 of IFIP Transactions, page 147-156. North-Holland, (1994)Uniform Parallelism Exploitation in Ordinary Programs.. ICPP, page 614-618. IEEE Computer Society Press, (1985)Applying an Abstract Data Structure Description Approach to Parallelizing Scientific Pointer Programs., , and . ICPP (2), page 100-104. CRC Press, (1992)Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor., , , , , , and . ICSAMOS, page 132-141. IEEE, (2008)Adapting cache line size to application behavior., , , , and . International Conference on Supercomputing, page 145-154. ACM, (1999)Author retrospective for a global resource-constrained parallelization technique., and . ICS 25th Anniversary, page 7-8. ACM, (2014)Abstract Description of Pointer Data Structures: An Approach for Improving the Analysis and Optimization of Imperative Programs., , and . LOPLAS, 1 (3): 243-260 (1992)Cache-aware partitioning of multi-dimensional iteration spaces., , , , and . SYSTOR, page 15. ACM, (2009)Performance Characterization of Itanium® 2-Based Montecito Processor., , , , , , and . SPEC Benchmark Workshop, volume 5419 of Lecture Notes in Computer Science, page 36-56. Springer, (2009)Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-uniform Iteration Spaces., , and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 17-32. Springer, (2005)