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Asymmetric-access aware optimization for STT-RAM caches with process variations., , , , and . ACM Great Lakes Symposium on VLSI, page 143-148. ACM, (2013)Accelerate context switch by racetrack-SRAM hybrid cells., , and . NANOARCH, page 115-116. ACM, (2016)A frequent-value based PRAM memory architecture., , , and . ASP-DAC, page 211-216. IEEE, (2011)Rapid design space exploration of two-level unified caches., , , and . ISCAS, page 1937-1940. IEEE, (2014)EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond., , , , and . CoRR, (2018)GNNSampler: Bridging the Gap Between Sampling Algorithms of GNN and Hardware., , , , , , , and . ECML/PKDD (5), volume 13717 of Lecture Notes in Computer Science, page 498-514. Springer, (2022)CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture., , , , and . HPCA, page 368-379. IEEE Computer Society, (2014)Adaptive placement and migration policy for an STT-RAM-based hybrid cache., , , , and . HPCA, page 13-24. IEEE Computer Society, (2014)PM3: Power Modeling and Power Management for Processing-in-Memory., , and . HPCA, page 558-570. IEEE Computer Society, (2018)3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis., , , , and . ICCD, page 254-259. IEEE Computer Society, (2009)