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A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS.

, , , , , and . ISSCC, page 198-199. IEEE, (2010)

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A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS., , , , , and . ISSCC, page 198-199. IEEE, (2010)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process., , and . A-SSCC, page 1-4. IEEE, (2015)A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS., and . CICC, page 1-4. IEEE, (2020)A wide-range DC/DC converter with 2nd order digital compensation and direct battery connection in 40nm CMOS., , , , and . CICC, page 1-4. IEEE, (2011)A 1.8 V pseudo-differential switched-capacitor amplifier., , , and . CICC, page 373-376. IEEE, (1998)A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from -50°C to 150°C in a 16nm FinFET process., , , , and . ESSCIRC, page 271-274. IEEE, (2015)5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm2 area., , , , and . ISSCC, page 102-103. IEEE, (2017)A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS., , and . CICC, page 1-4. IEEE, (2014)A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques., , , , and . IEEE J. Solid State Circuits, 52 (6): 1591-1604 (2017)