Author of the publication

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification.

, , , , , , , and . ISIC, page 344-347. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)A Shared Memory Module for Asynchronous Arrays of Processors., , and . EURASIP J. Embed. Syst., (2007)A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer., , , , , and . CICC, page 1-4. IEEE, (2015)NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (9): 1966-1978 (2020)Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism., , and . J. Intell. Inf. Syst., 62 (1): 163-189 (February 2024)An Asynchronous Convolution Process Engine forVGG-16 Neural Network., , , , and . ICTA, page 73-74. IEEE, (2020)High-Throughput Zipper Encoder for 800G Optical Communication System., , , , and . ICTA, page 214-215. IEEE, (2021)