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Timing- / Power-Optimization for Digital Logic Based on Standard Cells.

, , и . DSD, стр. 303-306. IEEE Computer Society, (2007)

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Heinrich Theodor Vierhaus

Rudolf Vierhaus

Stephan Vierhaus

Wolfgang Vierhaus

Henning Vierhaus

 

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Synchronization Fault Cryptanalysis for Breaking A5/1., , , и . WEA, том 3503 из Lecture Notes in Computer Science, стр. 415-427. Springer, (2005)Hardware/Software Based Hierarchical Self Test for SoCs., , , , , и . DDECS, стр. 159-160. IEEE Computer Society, (2006)Flip-Flops and Scan-Path Elements for Nanoelectronics., и . DDECS, стр. 307-312. IEEE Computer Society, (2007)Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience.. SPA, стр. 13. IEEE, (2018)Iterative error correction with double/triple error detection., и . SPA, стр. 14-19. IEEE, (2016)A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features., , и . IOLTS, стр. 241-246. IEEE Computer Society, (2005)An efficient on-line-test and back-up scheme for embedded processors., , и . ITC, стр. 964-972. IEEE Computer Society, (1999)Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration., , и . ARCS Workshops, том P-200 из LNI, стр. 251-262. GI, (2012)Generating reliable embedded processors., и . IEEE Micro, 18 (5): 33-41 (1998)Local microcode generation in system design., , , и . Code Generation for Embedded Processors, стр. 171-187. Kluwer, (1994)