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Relaxing state-access constraints in stateful programmable data planes.

, , , and . Comput. Commun. Rev., 48 (1): 3-9 (2018)

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DEMO: top-k cardinality estimation with HyperLogLog sketches., , , , and . ICIN, page 83-85. IEEE, (2021)Dependable Multicore Architectures at Nanoscale: The View From Europe., , , , , , , , , and 4 other author(s). IEEE Des. Test, 32 (2): 17-28 (2015)Demo: Implementing advanced network functions with stateful programmable data planes., , , , , and . LANMAN, page 1-2. IEEE, (2017)Feedback based droop mitigation., , , and . DATE, page 879-882. IEEE, (2011)Error detection in ternary CAMs using bloom filters., , , and . DATE, page 1474-1479. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Design of a QCA Memory with Parallel Read/Serial Write., , , , and . ISVLSI, page 292-294. IEEE Computer Society, (2005)FPGA oriented design of parity sharing RS codecs., , , and . DFT, page 259-265. IEEE Computer Society, (2005)Error Detection in Signed Digit Arithmetic Circuit with Parity Checker., , , , and . DFT, page 401-408. IEEE Computer Society, (2003)Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines., , , , , and . DFT, page 403-411. IEEE Computer Society, (2001)Error Detection and Correction in Content Addressable Memories., , and . DFT, page 420-428. IEEE Computer Society, (2010)