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Disambiguation of "Bhattacharyya, Shuvra S."

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Parameterized design framework for hardware implementation of particle filters.

, , and . ICASSP, page 1449-1452. IEEE, (2008)

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Somnath Bhattacharyya

Abinaschchandra Bhattacharyya

Arnab Bhattacharyya

Rameswar Bhattacharyya

Jyotirmay Bhattacharyya

 

Other publications of authors with the same name

Asynchrony and delay-insensitivity in computer engineering education.. WCAE@HPCA, page 7. ACM, (1999)A hybrid task graph scheduler for high performance image processing workflows., , , , and . GlobalSIP, page 634-637. IEEE, (2015)A Design Framework for Mapping Vectorized Synchronous Dataflow Graphs onto CPU-GPU Platforms., , , and . SCOPES, page 20-29. ACM, (2016)Archangel: A Hybrid UAV-based Human Detection Benchmark with Position and Pose Metadata., , , , , , , , , and . CoRR, (2022)Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems., , and . EURASIP J. Adv. Signal Process., 2003 (6): 565-579 (2003)Implementation of a high-throughput low-latency polyphase channelizer on GPUs., and . EURASIP J. Adv. Signal Process., (2014)An integrated hardware/software design methodology for signal processing systems., , , , , , , , , and 1 other author(s). J. Syst. Archit., (2019)Interface-based hierarchy for synchronous data-flow graphs., , and . SiPS, page 145-150. IEEE, (2009)Gradient Image Super-resolution for Low-resolution Image Recognition., , , , and . ICASSP, page 2332-2336. IEEE, (2019)Feature Extraction and Classification for Communication Channels in Wireless Mechatronic Systems., , , , , and . WFCS, page 107-110. IEEE, (2021)