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Delay optimization considering power saving in dynamic CMOS circuits.

, and . ISQED, page 364-369. IEEE, (2011)

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Delay optimization considering power saving in dynamic CMOS circuits., and . ISQED, page 364-369. IEEE, (2011)Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators., and . IEEE Trans. Aerosp. Electron. Syst., 49 (2): 706-715 (2013)Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection., , and . Integr., (2021)Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications., and . SoCC, page 109-112. IEEE, (2007)Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver., , and . ISCAS, page 2494-2497. IEEE, (2008)Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme., and . ISCAS, page 920-923. IEEE, (2009)A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder., , and . ISCAS (6), page 6142-6145. IEEE, (2005)Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations., and . VLSI Design, (2010)Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns., and . ISQED, page 111-116. IEEE Computer Society, (2003)BISTSYN - A Built-In Self-Test Synthesizer.. ICCAD, page 240-243. IEEE Computer Society, (1991)