( en | de | ru )

 

Disambiguation of "Sugibayashi, Tadahiko"

Author of the publication

copydeleteadd this publication to your clipboard
ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution.

, , , , , , , , , , , and . IRPS, page 1-4. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tadahiko Fujii

Tadahiko Iwashima

 

Other publications of authors with the same name

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor., , , , and . IEEE J. Solid State Circuits, 35 (8): 1153-1158 (2000)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2013)28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation., , , , , , , , , and 1 other author(s). IEICE Trans. Electron., 105-C (10): 627-630 (October 2022)A 16Mb MRAM with FORK Wiring Scheme and Burst Modes., , , , , , , , , and 5 other author(s). ISSCC, page 477-486. IEEE, (2006)Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors., , , , , and . ASICON, page 1-4. IEEE, (2013)Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode., , , , , and . IEICE Trans. Electron., 90-C (2): 531-535 (2007)A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)