( en | de | ru )

 

Disambiguation of "Pan, David Z."

Author of the publication

copydeleteadd this publication to your clipboard
An accurate sparse matrix based framework for statistical static timing analysis.

, , , , , and . ICCAD, page 231-236. ACM, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Weiqing Pan

 

Other publications of authors with the same name

Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 87-90. ACM, (2015)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)