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Disambiguation of "Zoni, Davide"

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BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers.

, , , , , and . J. Parallel Distributed Comput., (2017)

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Vladimir Zonine

Ioannis Zonios

Davide Cadamuro

Davide Pennino

Davide Batic

 

Other publications of authors with the same name

Thermal/performance trade-off in network-on-chip architectures., , and . ISSoC, page 1-8. IEEE, (2012)Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators., , , and . J. Syst. Archit., (2022)Exploring power reliability and performance aspects in on-chip networks for multi-cores.. Polytechnic University of Milan, Italy, (2014)Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments., , , , , , , and . PARMA-DITAM, volume 107 of OASIcs, page 6:1-6:11. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs., , and . IEEE Embed. Syst. Lett., 12 (1): 17-20 (2020)Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions., , , , and . ICECS, page 739-742. IEEE, (2019)A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures., , and . ARCS, volume 7179 of Lecture Notes in Computer Science, page 86-97. Springer, (2012)Consolidation of multi-tier workloads with performance and reliability constraints., , , and . HPCS, page 74-83. IEEE, (2012)BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers., , , , , and . J. Parallel Distributed Comput., (2017)A sensor-less NBTI mitigation methodology for NoC architectures., and . SoCC, page 340-345. IEEE, (2012)