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Variable-length VLIW encoding for code size reduction in embedded processors.

, , , , , and . SoCC, page 296-299. IEEE, (2016)

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Variable-length VLIW encoding for code size reduction in embedded processors., , , , , and . SoCC, page 296-299. IEEE, (2016)Power minimization for dynamic PLAs., , , and . ASP-DAC, page 1010-1013. ACM Press, (2005)On the integration of partitioning and global routing for rectilinear placement problems., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (1): 83-91 (1996)RSCE-aware ultra-low-voltage 40-nm CMOS circuits., , , , and . ISOCC, page 131-134. IEEE, (2011)Low power shift registers for megabits CMOS image sensors., , , and . ASICON, page 17-20. IEEE, (2011)Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS., , and . ISSCC, page 426-427. IEEE, (2013)Design of STR level converters for SoCs using the multi-island dual-VDD design technique., , , and . ISCAS, IEEE, (2006)Performance-driven technology mapping with MSG partition and selective gate duplication., and . ACM Trans. Design Autom. Electr. Syst., 11 (4): 953-973 (2006)Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling., , , and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 105-119. Springer, (2007)A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients., , , , , , , , , and . ASP-DAC, page 7-8. IEEE, (2022)