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A Calibratable Detector for Invasive Attacks.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1067-1079 (2019)

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Improving security in cache memory by power efficient scrambling technique., , and . IET Comput. Digit. Tech., 9 (6): 283-292 (2015)Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 80-89. Springer, (2003)On High-Quality, Low Energy BIST Preparation at RT-Level., , , , , and . LATW, page 52-57. IEEE, (2002)On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data., , , , and . DCIS, page 1-6. IEEE, (2022)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , and . J. Electron. Test., 16 (3): 193-202 (2000)Low power BIST by filtering non-detecting vectors., , , , , , , , , and . ETW, page 165-170. IEEE Computer Society, (1999)Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring., , and . VTS, page 124-129. IEEE Computer Society, (1996)A Calibratable Detector for Invasive Attacks., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1067-1079 (2019)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)A Highly Time Sensitive XOR Gate for Probe Attempt Detectors., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (11): 786-790 (2013)