( en | de | ru )

 

Disambiguation of "Zhang, Yichao"

Author of the publication

copydeleteadd this publication to your clipboard
Techno-Economic Selection of Energy Storage Providing Multiple Services.

, , , , , and . IECON, page 1-6. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yichao Yang

Yichao Huang

Zhang Zhang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Shuying Zhang

 

Other publications of authors with the same name

Traffic Classification of Network Security Agents Based on Feature Fusion Convolutional Neural Network., , and . CNML, page 196-200. ACM, (2023)Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster., , , , and . SAMOS, volume 14385 of Lecture Notes in Computer Science, page 241-254. Springer, (2023)Research on basic electro-mechanical performance of electroactive dielectric elastomer., , , and . ROBIO, page 762-767. IEEE, (2008)Techno-Economic Selection of Energy Storage Providing Multiple Services., , , , , and . IECON, page 1-6. IEEE, (2022)Knowledge Diffusion in Complex Networks., , , , and . UIC/ATC/ScalCom, page 1139-1143. IEEE Computer Society, (2015)A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR., , , , , and . CoRR, (2024)DeepSeek LLM: Scaling Open-Source Language Models with Longtermism., , , , , , , , , and 76 other author(s). CoRR, (2024)An exponential triangle model for the Facebook network based on big data., , , and . INDIN, page 992-996. IEEE, (2017)TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios., , , , , and . ACM Great Lakes Symposium on VLSI, page 86-91. ACM, (2024)Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET., , , , , , , , , and 4 other author(s). CoRR, (2024)