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Disambiguation of "Alioto, Massimo"

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High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.

, and . ISCAS, page 2998-3001. IEEE, (2007)

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Massimo Viola

Massimo Malagó

Massimo Tallarida

Massimo Moser

Massimo Busin

 

Other publications of authors with the same name

A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm., , , and . A-SSCC, page 301-304. IEEE, (2017)Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations., , , , and . ISCAS, page 2043-2046. IEEE, (2011)Power-delay trade-offs in SCL gates., and . ISCAS (3), page 249-252. IEEE, (2002)A technique to design high entropy chaos-based true random bit generators., , , , and . ISCAS, IEEE, (2006)Analysis of layout density in FinFET standard cells and impact of fin technology.. ISCAS, page 3204-3207. IEEE, (2010)Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS., , , and . ISSCC, page 482-484. IEEE, (2012)The Internet of Things on Its Edge: Trends Toward Its Tipping Point., and . IEEE Consumer Electron. Mag., 7 (1): 77-87 (2018)Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes., , and . AICAS, page 1-5. IEEE, (2023)38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems., , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)