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A Method of Via Variation Induced Delay Computation., , , , , , , and . DATE, page 1712-1713. IEEE, (2020)Multiple constant multiplication implementations in near-threshold computing systems., , and . ICASSP, page 1071-1075. IEEE, (2015)Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization., , and . ASAP, page 100-107. IEEE Computer Society, (2014)Provably minimal energy using coordinated DVS and power gating., , , and . DATE, page 1-6. European Design and Automation Association, (2014)A temperature-aware synthesis approach for simultaneous delay and leakage optimization., and . ICCD, page 316-321. IEEE Computer Society, (2013)Gate sizing in the presence of gate switching activity and input vector control., , and . VLSI-SoC, page 138-143. IEEE, (2013)Gate Sizing Under Uncertainty., , and . VLSI-SoC (Selected Papers), volume 461 of IFIP Advances in Information and Communication Technology, page 23-47. Springer, (2013)Maximizing yield in Near-Threshold Computing under the presence of process variation., , , and . PATMOS, page 1-8. IEEE, (2013)Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.. University of California, Los Angeles, USA, (2014)