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Disambiguation of "de la Rosa, José M."

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Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1677-1682 (March 2024)

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José Manuel la Rosa Vázquez

Jonatan Núñez-de la Rosa

Jonatan Núñez de la Rosa

José Gabriel la Rica

Maurus la Rosa

 

Other publications of authors with the same name

Hybrid continuous-time/discrete-time circuit techniques for the efficient implementation of wideband ΣΔ ADCs., and . MWSCAS, page 374-377. IEEE, (2012)A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS., , and . VLSI-SoC, page 47-52. IEEE, (2012)Lessons Learned the Hard Way., , , , , , , , , and 23 other author(s). ISCAS, page 1-18. IEEE, (2020)Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices., , , , and . ISCAS, page 1-5. IEEE, (2021)Using nanoHUB.org for teaching and learning nanoelectronic devices in materials engineering.. EDUCON, page 1-4. IEEE, (2012)A Low-Input Capacitance 12-bit SAR ADC for use in Self-Powered IoT Nodes., , , and . ISCAS, page 2640-2644. IEEE, (2022)Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass Sigma-Delta modulators., , , , and . ISCAS (1), page 340-343. IEEE, (2001)A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers., , and . ISCAS, page 2950-2953. IEEE, (2007)Bulk-Input VCO-Based Sigma-Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS., and . ISCAS, page 1-5. IEEE, (2019)Behavioral Modeling of SAR ADCs in Simulink., , , , and . ISCAS, page 1-5. IEEE, (2018)