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18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , и . ESSCIRC, стр. 210-213. IEEE, (2010)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , и . ESSCIRC, стр. 177-180. IEEE, (2012)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , и . VLSIC, стр. 118-119. IEEE, (2012)A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI., , , и . VLSI Circuits, стр. 1-2. IEEE, (2021)Guest Editorial 2021 Custom Integrated Circuits Conference., и . IEEE J. Solid State Circuits, 57 (3): 675-676 (2022)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET., , , , , , , , , и 9 other автор(ы). ESSCIRC, стр. 259-262. IEEE, (2021)Phase Noise Compensation for OFDM Systems Exploiting Coherence Bandwidth., , , и . SPAWC, стр. 1-5. IEEE, (2019)Minimum-power retiming for dual-supply CMOS circuits., , и . Timing Issues in the Specification and Synthesis of Digital Systems, стр. 43-49. ACM, (2002)A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS., , , , , , , , , и . ISSCC, стр. 328-329. IEEE, (2010)19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers., , , , , , , , , и 14 other автор(ы). ISSCC, стр. 304-306. IEEE, (2020)