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1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS., и . VLSIC, стр. 144-145. IEEE, (2012)An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages., и . ISCAS, стр. 3973-3976. IEEE, (2010)Charge-pump reducing current mismatch in DLLs and PLLs., и . ISCAS, IEEE, (2006)A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator., , и . ISCAS (5), стр. 373-376. IEEE, (2002)A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme., , и . ISCAS (1), стр. 461-464. IEEE, (2002)All-digital hybrid temperature sensor network for dense thermal monitoring., , , , , и . ISSCC, стр. 260-261. IEEE, (2013)A clock delayed sleep mode domino logic for wide dynamic OR gate., и . ISLPED, стр. 176-179. ACM, (2003)SPAF: Sub-texel Precision Anisotropic Filtering., , и . Workshop on Graphics Hardware, стр. 99-107. The Eurographics Association, (2001)A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (8): 733-737 (2016)A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1564-1568 (2018)