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Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS., , , , , , , and . EuCNC, page 434-439. IEEE, (2022)Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins., , , and . DDECS, page 122-126. IEEE, (2017)Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures., , , , and . ASYNC, page 78-85. IEEE, (2020)Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops., , , , and . DSD, page 616-621. IEEE, (2020)Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops., , , and . DSD, page 639-642. IEEE, (2019)HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken., , , , and . MBMV, page 137-145. Universitätsbibliothek Berlin, Germany, (2009)Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle., , , , and . DDECS, page 9-14. IEEE, (2018)Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip., , , and . DCIS, page 1-6. IEEE, (2018)Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting., , , and . IEEE Access, (2022)Machine Learning Approach for Accelerating Simulation-based Fault Injection., , , , , and . NorCAS, page 1-6. IEEE, (2021)