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Stand-by low-power architecture in a 3 V-only 2-bit/cell 64-Mbit flash memory.

, , , and . ICECS, page 929-932. IEEE, (2001)

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Design space exploration of latency and bandwidth in RRAM-based solid state drives., , , , and . NVMTS, page 1-4. IEEE, (2015)An Error Control Code Scheme for Multilevel Flash Memories., , , and . MTDT, page 45-50. IEEE Computer Society, (2001)Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND., , , , , , , , , and 3 other author(s). IRPS, page 1-8. IEEE, (2023)Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance., , , and . Proc. IEEE, 105 (9): 1589-1608 (2017)Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage., , , and . Future Internet, 15 (10): 319 (2023)Construction of polyvalent error control codes for multilevel memories., , , and . ICECS, page 751-754. IEEE, (2000)Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes., , , , , and . ITW, page 1-5. IEEE, (2019)Hierarchical Sector Biasing Organization for Flash Memories., , , , and . MTDT, page 29-33. IEEE Computer Society, (2000)SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives., , , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Program word-line voltage generator for multilevel flash memories., , , , and . ICECS, page 1030-1033. IEEE, (2000)