( en | de | ru )

 

Disambiguation of "Shibata, Yuichiro"

Author of the publication

copydeleteadd this publication to your clipboard
Stream Computation of 3D Approximate Convex Hulls with an FPGA.

, , , , , , , , and . HEART, page 69-75. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Daisuke Shibata

Tomohiro Shibata

Yuichiro Honda

 

Other publications of authors with the same name

Documents as a Bag of Maximal Substrings - An Unsupervised Feature Extraction for Document Clustering., , and . ICEIS (1), page 5-13. SciTePress, (2011)A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs., , and . CISIS, volume 993 of Advances in Intelligent Systems and Computing, page 453-461. Springer, (2019)Retrieving 3-d information with FPGA-based stream processing., , , , and . FPGA, page 261. ACM, (2008)Unsupervised Segmentation of Bibliographic Elements with Latent Permutations., , and . WISE Workshops, volume 6724 of Lecture Notes in Computer Science, page 254-267. Springer, (2010)Light-Weight Fine-Grain Dynamic Partial Reconfiguration on Xilinx FPGAs., , and . CISIS, volume 772 of Advances in Intelligent Systems and Computing, page 518-526. Springer, (2018)Reconfigurable Systems: New Activities in Asia., , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 585-594. Springer, (2000)Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA., , and . Asia-Pacific Computer Systems Architecture Conference, volume 2823 of Lecture Notes in Computer Science, page 54-68. Springer, (2003)Evaluation of Space Allocation Circuits., , , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 428-437. Springer, (2005)An FPGA-based Power-saving Particle Filter Using Dynamic Reconfiguration., , , and . CANDAR (Workshops), page 439-443. IEEE, (2021)A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis., , , , and . SIGARCH Comput. Archit. News, 42 (4): 69-74 (2014)