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A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions.

, , , and . ISMVL, page 372-381. IEEE Computer Society, (1991)

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Reducing the Cost of Test Pattern Generation by Information Reusing., , and . ICCD, page 310-313. IEEE Computer Society, (1993)A High-Performance Hardware-Efficient Memory Allocation Technique and Design., , and . ICCD, page 274-276. IEEE Computer Society, (1999)A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions., , , and . ISMVL, page 372-381. IEEE Computer Society, (1991)Step-Wise Synthesis of CCD MVL Functions., , and . ISMVL, page 300-307. IEEE Computer Society, (1990)Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm., , and . ISMVL, page 216-221. IEEE Computer Society, (1995)Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic Network Realization., and . ISMVL, page 58-64. IEEE Computer Society, (1994)A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits., and . ISMVL, page 15-20. IEEE Computer Society, (2001)A Heuristic-Based Wormhole Routing Algorithm for Hypercube Multicomputer Networks., , and . Clust. Comput., 4 (3): 253-262 (2001)Digital circuit design through simulated evolution (SimE)., , , and . IEEE Congress on Evolutionary Computation, page 375-381. IEEE, (2003)Fault Tolerance in Topological Optimization of Computer Networks., and . CATA, page 84-87. ISCA, (2003)