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Disambiguation of "Delgado-Frias, José G."

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Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories.

, and . ISCAS, page 2786-2789. IEEE, (2007)

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José Onelio Blanco Delgado

Armando José Oropeza Delgado

José Miguel Martins Delgado

Humberto Jorge José

Nadine José Gonzalez

 

Other publications of authors with the same name

Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories., and . ISCAS, page 2786-2789. IEEE, (2007)Superpipelined reconfigurable hardware for DSP., and . ISCAS, IEEE, (2006)BASIS: A Biological Approach to System Information Security., , , , , , and . MMM-ACNS, volume 2052 of Lecture Notes in Computer Science, page 127-142. Springer, (2001)Executing tree routing algorithms on a high-performance pattern associative router., , and . J. Syst. Archit., 44 (11): 849-866 (1998)A High Performance Hybrid Wave-Pipelined Multiplier., and . ISVLSI, page 282-283. IEEE Computer Society, (2005)Multipath Routing Based Secure Data Transmission in Ad Hoc Networks., and . WiMob, page 17-23. IEEE Computer Society, (2006)A mesochronous pipeline scheme for high performance low power digital systems., and . ISCAS, IEEE, (2006)An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice., and . CCWC, page 1-4. IEEE, (2017)CNTFET SRAM cell with tolerance to removed metallic CNTs., and . MWSCAS, page 186-189. IEEE, (2012)BVE: a wafer-scale engine for differential equation computation., and . ICS, page 101-107. ACM, (1988)