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Disambiguation of "Bhanja, Sanjukta"

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Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)

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Nilendra Nath Bhanja

 

Other publications of authors with the same name

MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells., , and . JETC, 13 (1): 2:1-2:15 (2016)Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)MatlabHTM: A sequence memory model of neocortical layers for anomaly detection., , and . SoftwareX, (2020)A Qualitative Expert System for Clinical Trial Assignment., , , , and . FLAIRS, page 84-88. AAAI Press, (1998)Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks., , and . VLSI Design, page 586-591. IEEE Computer Society, (2005)An Error Model to Study the Behavior of Transient Errors in Sequential Circuits., and . VLSI Design, page 485-490. IEEE Computer Society, (2009)Non-destructive variability tolerant differential read for non-volatile logic., , and . MWSCAS, page 178-181. IEEE, (2012)Causal probabilistic input dependency learning for switching model in VLSI circuits., and . ACM Great Lakes Symposium on VLSI, page 112-115. ACM, (2005)An Accurate Probalistic Model for Error Detection., and . VLSI Design, page 717-722. IEEE Computer Society, (2005)CNT logic knowledge module integrated in digital CMOS logic design course., and . MSE, page 115-117. IEEE Computer Society, (2009)