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Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction., , , , and . IEEE Trans. Circuits Syst. Video Techn., 30 (2): 387-399 (2020)Asynchronous Spiking Pixel With Programmable Sensitivity to Illumination., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3854-3863 (2018)On the design of a sparsifying dictionary for compressive image feature extraction., , , and . ICECS, page 689-692. IEEE, (2015)An ultra-low-power voltage-mode asynchronous WTA-LTA circuit., , and . ISCAS, page 1817-1820. IEEE, (2013)On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique., , and . ISCAS, page 1102-1105. IEEE, (2015)A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics., , and . ISCAS, page 2626-2629. IEEE, (2013)Hardware-oriented feature extraction based on compressive sensing., , and . ICDSC, page 211-212. ACM, (2015)A bio-inspired two-layer mixed-signal flexible programmable chip for early vision., , , , , , , and . IEEE Trans. Neural Networks, 14 (5): 1313-1336 (2003)Flydeling: Streamlined Performance Models for Hardware Acceleration of CNNs through System Identification., , , , and . ACM Trans. Model. Perform. Evaluation Comput. Syst., 8 (3): 1-33 (September 2023)Switched-capacitor networks for scale-space generation., , , , , and . ECCTD, page 190-193. IEEE, (2011)