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Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading.

, , and . PACT, page 313-324. IEEE Computer Society, (2009)

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Symbiotic jobscheduling for a simultaneous multithreaded processor, and . SIGARCH Comput. Archit. News, 28 (5): 234--244 (November 2000)Exploring the Potential of Architecture-Level Power Optimizations., and . PACS, volume 3164 of Lecture Notes in Computer Science, page 132-147. Springer, (2003)Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management., , and . IEEE Micro, 39 (3): 75-83 (2019)The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU., and . MICRO, page 281-293. ACM, (2015)Pointer cache assisted prefetching., , , and . MICRO, page 62-73. ACM/IEEE Computer Society, (2002)Hardware Identification of Cache Conflict Misses., and . MICRO, page 126-135. ACM/IEEE Computer Society, (1999)Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy., , , and . MICRO, page 183-194. IEEE Computer Society, (2004)Control Flow Optimization Via Dynamic Reconvergence Prediction., , and . MICRO, page 129-140. IEEE Computer Society, (2004)Reducing power with dynamic critical path information., , and . MICRO, page 114-123. ACM/IEEE Computer Society, (2001)Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors., , , and . SIGMETRICS/Performance, page 169-180. ACM, (2009)